Change-Id: I1886e750d806be2e86246e8e199f395e13ff444b
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>

Change-Id: I15fa0818b1ed6b2e5b05b5ffd1a5196d832a597b
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>

Change-Id: I7018cf1d7a9cdc63f9a69fa7db6e37e4b591e1b3
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>

This adds support for the Librem 11 tablet, using the ME binary from
the original BIOS and FSP binaries from a Jasper Lake Chromebook.

The following features were tested with PureOS:
* Audio (speakers, microphone, headset jack)
* Cameras
* Display
* Touchscreen and pen
* Keyboard cover, with tablet/laptop mode switch indicated via ACPI
* Power and volume buttons
* USB-C ports (USB 2/3, DP alt mode, PD charging)
* SD card reader
* WLAN
* Bluetooth
* NVMe SSD (socketed)
* Battery state information from EC
* Accelerometer

A UART is accessible with soldering via test points on the mainboard,
documented in the mainboard Kconfig with a toggle to enable it for
coreboot logging.

Change-Id: I545994889ddfb41f56de09b3a42840bccbd7c4aa
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>

Change-Id: Ibb38f620bef09c71ca47323f574004e73d40f834
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>

This reverts commit 21e61847.

Setting an MTRR in early_ramtop_enable_cache_range() causes
FspMemoryInit to fail with EFI_UNSUPPORTED on all tested FSP binaries
for Jasper Lake.

Change-Id: Ia353a693cee4d088efbd3073e88b2317309697a8
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>

Jasper Lake was missing these bases, so attempting to enable an SCI
would poke unrelated registers starting from offset 0.  Set them so
GPEs can be enabled.

Change-Id: Ib6b9b9a79e9cc4467e609eaf591ec4e87b78d617
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>

Separate these so a mainboard can describe a PS/2 keyboard without a
PS/2 mouse or vice-versa.

Librem 11 has a PS/2 keyboard for the volume keys, but does not have a
PS/2 mouse, and the presence of a mouse device can cause the cursor to
appear on the desktop incorrectly.

ps2_controller.asl remains since many boards include it, it now just
includes the two new files.

Change-Id: I13a4c2caf8dc9e5004b775dc0a9ac2488e39f184
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>

Librem 11's volume keys act as a PS/2 keyboard with only those two
keys.  Reduce the minimum number of top-row keys to 2.  Make the
"rest of keys" (alphanumerics, punctuation, etc.) optional.

Change-Id: Idf80b184ec816043138750ee0a869b23f1e6dcf2
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>

Three boards have copies of this macro, and intelp2m already generates
pad configurations using it.  Move the definition to gpio_defs.h.

Change-Id: If09180e191de9a959c3ab62381b6824e4f897277
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>

Support generating Jasper Lake GPIO configuration from inteltool logs

Change-Id: I519d27e0c91c8d9159224d9bc1c6e49c83270b7a
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>

Enable HDMI1 output, which corresponds to the physical DisplayPort
connector, so passive adapters to DVI or HDMI will work with native
graphics init.

Change-Id: I95a147978697f4af092fe61ceacd2e725155d489
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>

Linux uses the century byte if it's any value over 20.  Don't put
ramtop there, and reserve the byte.

Change-Id: I73f82b5cbe93b858217323f974b2d92b93407346
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>

The Librem Mini v1/v2 board option to enable automatic power on was
changed to a CMOS layout when upstreamed.  Rework build.sh, the board
configurations, and the preconfigures to use nvramtool altering
cmos.default in CBFS.

Change-Id: Ic265aa572e5def1b778898fc7eeaad699ae021a8
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>

Since e633d370, cmos.layout for Cannon Lake boards must have a ramtop
entry.

Change-Id: I2bf71f2dd79f2e1e2e13f62a3e08103336bbad61
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>

Update repo for new KBL, CFL, CML microcode.

Change-Id: I0355a8b1661a950bcf90fc4870b95cc1dad9a1c7
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>

Quote expansions not intended to word-split, split up local declaration
and assignment, test command success directly, use $(..) instead of
backticks.

Change-Id: I67a60c3869defc2a2c76b7afbc78ce407e8f6b8f
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>

coreboot_util.sh now checks the entire ROM, not just the BIOS region.
The ifdtool invocation produces a warning with no platform, and it does
not work correctly on 32 MB images.  Remove it.

Change-Id: I375be54f7c31209513869f98e6d37746104718ec
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>

Add 8 second boot delay in SeaBIOS for L1UM v2 as well as Mini v1/v2.

Change-Id: Ie0f94582fca3044fe5c1aebcadac192de3dc8cf2
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>

Remove VGA BIOS, use coreboot native graphics init instead.

Change-Id: I96dcb16b2de60a6cb07a89416ebc74d8f61923ef
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>

Matt DeVillier authored 5 years ago and Jonathon Hall committed 1 year ago

Change-Id: I1ea470ce710a3d32cc0e5a3be591dff343be1932
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

Matt DeVillier authored 4 years ago and Jonathon Hall committed 1 year ago

Checking the CSE device status before printing means it will skip
printing for devices with the ME disabled, leaving the user no easy
way to verify the ME is properly disabled. Remove the check.

Test: build/boot Librem Mini, verify ME status printed as expected
on device with disabled/neutered ME.

Change-Id: I939333199aa699039fec727beb094e4eb2ad7149
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

Matt DeVillier authored 4 years ago and Jonathon Hall committed 1 year ago

Checking the CSE device status before printing means it will skip
printing for devices with the ME disabled, leaving the user no easy
way to verify the ME is properly disabled. Remove the check.

Test: build/boot Librem 13v4, verify ME status printed as expected
on device with disabled/neutered ME.

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: Iaa4f4a369d878a52136c3479027443ea4e731a36

Matt DeVillier authored 6 years ago and Jonathon Hall committed 1 year ago

1) Patch to not start in console mode if a bootsplash image is to be
displayed, eliminating the flicker from starting in conole mode then
immediately switching to the bootslpash.

2) Patch to not exit the boot menu via ESC once shown. This is a user-
requested feature to prevent accidentally exiting the boot menu by
spamming the ESC key.

3) Patch to show 'Booting From USB Device' vs 'Booting from Hard Disk'
when booting from USB-attached storage devices.

Adjust application of patch file so as to make for a reproducible build.
The committer name, email and date needs to match the author's
otherwise on every build, seabios will have a different commit
hash for HEAD, which can be problematic for reproducable builds
but also could confuse people if every time they type 'make', they
get a different hash of their rom

Change-Id: I32f13827b8b26d98cadc68065894674bf157c906
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

SB patch

Change-Id: I03b9a92895114a961035e4ebe1a1146a3baa2c8b
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

Matt DeVillier authored 5 years ago and Jonathon Hall committed 1 year ago

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I449f4c6f4abcf3d8dcea12f62ca19215098dd29d

This adds support for booting the Librem L1UM v2 mainboard with
coreboot, using binaries from the original BIOS.

The following features have been tested on PureOS:
- USB: front USB3, rear USB3, USB2 header on board
- SATA: 8x SATA ports, one M.2 M-key shared with SATA0
- PCIe: two PEG slots, one PCIe slot from PCH, and one M.2 M-key
- Network: 2x GbE
- Video: BMC VGA and IPMI
- Serial: Physical serial port, provided by BMC SuperIO
- Hardware monitor
- POST code display
- TPM2

These binaries are extracted from the original BIOS:
- Intel Management Engine
- Intel Firmware Descriptor

This was developed and tested on a Librem L1UM v2 using a Core i7-9700
CPU.  Native graphics init works for the Aspeed AST2500 BMC.

For development, the serial port console works from bootblock.  Early
init waits for the BMC to finish booting since this is required for
serial port output.

Change-Id: I990f6024d65098a9553d7d1fe7f36614cc55ea19
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>

Matt DeVillier authored 6 years ago and Jonathon Hall committed 1 year ago

Required since we don't have our own fork of the
3rdparty submodules repositories (and have no need to)
in order to build without referencing the upstream repo

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: Id51a66938dd749fd884cdf3c4df40402854fce6f

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ice46117ccd3a082e20ce0d18421fd7da92aa3dbf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77330


Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ie3c131db52993d99994e0d9cc04b80f480a72ab8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77335


Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Move specific options under the boolean and remove dummy
SOC_SPECIFIC_OPTIONS.

Change-Id: I6ae52ceb61489e5a050a60d1fbbf4250960407eb
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76487


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>

This will include this new commit:

 * Add GenoaPI 1.0.0.4 blobs

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I216580653ed22d961fa4d79622fdcc3985c36316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77355


Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

According to the schematic, karis does not have a WFC.

BUG=b:294155897
TEST=emerge-rex coreboot

Change-Id: I9b4ecf2e96c77c131a60e48614d792370dd33423
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77283


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>

Allows coolstar's Windows overlay drivers to attach, while not affecting
operation under Linux or ChromeOS

TEST=build/boot Win11, Linux 6.x on google/drallion

Change-Id: I30ab2e9da00743c4d7086aac94652be46040f36d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77305


Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Allows the EC to be properly notified of type-c events like charger
wattage too low (eg),

TEST=build/boot Win11, Linux 6.x on google/drallion

Change-Id: I7a4130cf6f8c24e3f91e327adf1f3e563322c0af
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77282


Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Set the USCI device scope to _SB and set HID to USBC000 so Windows
driver attaches. This matches the ACPI used by the non-Chromebook
version of the Dell Latittude 7410 (which uses the same EC).

TEST=build/boot Win11 on google/drallion

Change-Id: If482fa4a4856c7bc085795bc72b35ebefe2f15c4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77281


Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Allows coolstar's Windows drivers to attach.

TEST=build/boot Win11 on google/drallion

Change-Id: Idd339811563cd2cdfc4cc31bc5660a62f4e36a66
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77280


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>

Both Windows and MacOS get cranky if the Mutex synclevel is non-zero,
aborting any Acquire() call with Mutex param that has a non-zero
synclevel.

TEST=build/boot Win11 on google/drallion, verify DPTF driver loaded and
functional.

Change-Id: Ie77e9ed04658b508b2063ae219afcdc0ac465c58
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77279


Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

The RPL PCH uses a different ACPI Device ID than ADL PCH.

Ref: Intel 700 Series Chipset Family PCH Datasheet, Volume 1 (#743835)
Change-Id: I03f47a43ff985213ad617e834db7f974f687d877
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77150


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

Add 4.22 template and update index.

Change-Id: Id44616ca70ba693fc622164469bb748ee269565b
Signed-off-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77277


Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

The doc.coreboot.org container is several years out of date, using the
three year old Alpine 3.8 as the base image along with Sphinx related
pip packages which are even older. Accordingly, update the documentation
related pip packages in the coreboot-jenkins-node container as well.

- Update doc.coreboot.org to Alpine 3.18.3
- Update documentation related pip packages on coreboot-jenkins-node
  and doc.coreboot.org to the latest versions on PyPI
- Update Sphinx to 6.2.1 as the latest version of sphinx_rtd_theme does
  not yet support sphinx >= 7

The updates also noticeably improve performance, dropping documentation
build times from ~75 s down to ~42 s on my system from the Alpine+Python
updates alone, and further down to ~35 s with the rest of the updates.

TEST: The documentation builds and renders properly when built using the
updated container.

Change-Id: I38dfd22ee71c3779ab5fd3b3060e4675e9e3fe54
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73159


Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>