• Max Filippov's avatar
    target-xtensa: implement MISC SR · b7909d81
    Max Filippov authored
    The Miscellaneous Special Registers Option provides zero to four scratch
    registers within the processor readable and writable by RSR, WSR, and
    XSR. These registers are privileged. They may be useful for some
    application-specific exception and interrupt processing tasks in the
    kernel. The MISC registers are undefined after reset.
    See ISA, 4.7.3 for details.
    Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
    Signed-off-by: default avatarBlue Swirl <blauwirbel@gmail.com>
overlay_tool.h 17.3 KB