The one in the `dummyflasher` is a little peculiar. We actually never
knew the type of the `st_size` field in `struct stat`. It happens to
be `signed` in some systems (e.g. DJGPP).

Change-Id: If36ba22606021400b385ea6083eacc7b360c20c5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/35800


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Only minor differences in the Firmware Descriptor, compared to their
predecessors.

We extend our check on the `ICCRIBA` field in the descriptor to dis-
tinguish it from older generation. Alas, the `freq_read` field was
repurposed, so we can't use it as sanity check any more.

Change-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34072


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>

Mostly by changing to `unsigned` types where applicable, sometimes
`signed` types, and casting as a last resort.

Change-Id: I08895543ffb7a48058bcf91ef6500ca113f2d305
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/30409


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>

It's almost identical to 100 series PCHs and later. There are some
additional FREGs (12..15). To not clutter the `if` conditions further,
make more use of `switch` statements.

Tested on Kontron mAL10. Mark it as DEP as usually the last sector
is not covered by the descriptor layout and can't be read.

Change-Id: I1c464b5b3d151e6d28d5db96495fe874a0a45718
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/30995


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

None of these functions are used outside of the files they are defined
in, so make them all static.

Change-Id: Ie9cbe12d289bcedacf2f1bf483ae64ef8039ccc1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33667


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>

This should provide more flexibility while we don't have to allocate
256B extra per layout entry.

Change-Id: Ibb903113550ec13f43cbbd0a412c8f35fe1cf454
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33515


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

Change-Id: Ia895e35edfc86b6955395c4570d67477da70e2c7
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33256


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

GCC is picky about the comment being where the break should go.

Change-Id: I05db2fb34025fefe2c6ddd1274c8e45b7cc5a4b6
Signed-off-by: Richard Hughes <richard@hughsie.com>
Reviewed-on: https://review.coreboot.org/c/30406


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Change-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25381


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

This adds PCI IDs for C620-series PCHs and adds
CHIPSET_C620_SERIES_LEWISBURG as a new entry in the ich_chipset enum.

Lewisburg is very similar to Sunrise Point for Flashrom's purposes,
however one important difference is the way the "number of masters" is
interpreted from the flash descriptor (0-based vs. 1-based). There are
also new flash regions defined.

Change-Id: I96c89bc28bdfcd953229c17679f2c28f8b874d0b
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/20922


Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

`ssize_t` is a POSIX type (cf. IEEE Std 1003.1).

Change-Id: I5f6f114523f541b3a8d845c6faee2c0b9f753bae
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reported-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-on: https://review.coreboot.org/21015


Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Urja Rannikko <urjaman@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Change-Id: Id28cb3abc45c6e7f4c4accfc019579c7448c45d7
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20247


Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Interpretation of component clocks changed. Also more regions and more
masters are supported now. The number of regions (NR) is now static per
chipset (10 in the 100 Series case) and not coded into the descriptor
any more.

v2: o Use guess_ich_chipset() for read_ich_descriptors_from_dump().
    o Update region extraction in `ich_descriptors_tool`.

TEST=Run `ich_descriptors_tool` over a 100 Series dump and checked
     that output looks sane. Run `ich_descriptors_tool` over dumps
     of five different older systems (1 x Sandy Bridge, 3 x Ivy Bridge,
     1 x Haswell). Beside whitespace changes, regions not accounted
     by `NR` are not printed any more.

Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18973


Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Add guess_ich_chipset() that takes fields from a descriptor dump and
returns the lowest possible chipset version.

Intel did several incompatible changes to the descriptor through the
years. However, they forgot to add a version number. So we have to
apply some heuristics to detect the chipset version in case of exter-
nal flashing.

Change-Id: Ie1736663dc33801b19d3e695c072c61a6c6345a2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20246


Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

The condition `base > limit` is still valid since `base` is always at
least 4096 greater than `limit` in this case.

Change-Id: I11ac0a50b3f32f47879e7cfb7a26068cd0572ede
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19046


Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

The Sunrise Point PCH, paired with Skylake, has some minor changes
in the HW sequencing interface:

  * Support for more flash regions moved PR* registers
  * Only 4KiB erase blocks are supported by the primary erase command
  * A second erase command for 64KiB pages was added
  * More commands were added for status register access etc.
  * A "Dedicated Lock Bits" register was added

No support for the new commands was added.

The SW sequencing interface seems to have moved register location and
is not supported any more officially. It's also untested.

Changes are loosely based on the Skylake support commit in Chromium OS
by Ramya Vijaykumar:

  commit a9a64f9e4d52c39fcd3c5f7d7b88065baed189b1
  Author: Ramya Vijaykumar <ramya.vijaykumar@intel.com>

      flashrom: Add Skylake platform support

Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18962


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>

Add a guard around read_ich_descriptors_via_fdo() which uses raw
hardware access and is only called from `ichspi`.

Fixes linking in case `NEED_RAW_ACCESS != 1`.

Change-Id: I5a35c607df44cdbcbacb960f8922c1bf9f1f2002
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20265


Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

The subtle difference was ignored when adding these chipsets. The
integrated Wildcat Point LP PCH is documented in [1].

I'm not sure how to account for "Broadwell H" which seems not publicly
documented. Maybe it's an unreleased HM9*, in which case the non-LP
path should be correct.

[1] Mobile 5th Generation Intel® Core(TM) Processor Family I/O,
    Intel® Core(TM) M Processor Family I/O, Mobile Intel® Pentium® Processor
    Family I/O, and Mobile Intel® Celeron® Processor Family I/O Datasheet
    Revision 004
    Document Number: 330837

Change-Id: I6b7ca3c0bde111b04ed7c745ed76d28d3d05f01c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18883


Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

+1 on everything doesn't make software greater per se.

v2: o Fix another +1.
    o Amend style of similar (not +1 suffering) code, too.

Change-Id: Ifa5455c999e90ff9121aed29f542d71ac9ca2b1c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19044


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Add an option --ifd to read the ROM layout from an Intel Firmware
Descriptor (IFD). Works the same as the -l option, if given, -i
specifies the images to update.

v2: o Rebased on libflashrom, use libflashrom interface.
    o Use functions from ich_descriptors.c.

v3: o Move ich_descriptors.o to LIB_OBJS, thus build it independent
      of arch and programmers.
    o Bail out if we aren't compiled for little endian.
    o Update flashrom.8.tmpl.

v4: o Incorporated David's comments.
    o Removed single-character `-d` option.

v5: Changed region names to match the output of `ifdtool --layout ...`

Change-Id: Ifafff2bf6d5c5e62283416b3269723f81fdc0fa3
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17953


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

I didn't really know what I was doing and hope removing the #ifdefs
doesn't have negative side effects.

The idea is to make the functions generally available for external
flashing (e.g. you might want to flash an Intel machine using an ARM
device as programmer).

Beware of big endian trouble, I guess. :-P

Change-Id: Ib3d38a622a581afee87b49777e775942cc901fc8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17952


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

These explicit off-by-one calculations were... off-by-one.

Change-Id: If57c92ba28f91c4d72123ef0cfd2d9d5ac0a0656
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19031


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>

Silvermont (Bay Trail, Rangeley, Avoton) seems to still use the old
density encoding with 3 bits per chip. Documentation is unavailable
(held concealed by Intel) but thanks to the efforts of Tai-Hong
(Type) Wu the layout is clear now. This patch is based on his one
but solves the issue differently thus reducing the code complexity.

Corresponding to flashrom svn r1861.

Signed-off-by: Tai-Hong Wu <thwu@lunartoday.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

The Wildcat Point PCH can be paired with Broadwell or Haswell.
This patch was essentially backported from ChromiumOS commit 9bd2af8.

Corresponding to flashrom svn r1845.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

The core of this patch to support Bay Trail originally came from the
Chromiumos flashrom repo and was modified by Sage to support the
Rangeley/Avoton parts as well.
Because that was not complicated enough already Stefan Tauner refactored
and refined everything. Bay Trail seems to be the first Atom SoC able to
support hwseq. No SPI Programming Guide could be obtained so it is
handled similarly to Lynx Point which seems to be its nearest relative.

Corresponding to flashrom svn r1844.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested-by: Marc Jones <marcj303@gmail.com>
Tested-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested-by: Thomas Reardon <thomas_reardon@hotmail.com>
Tested-by: Wen Wang <wen.wang@adiengineering.com>
Acked-by: Marc Jones <marcj303@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

Possible values as well as encodings have changed in newer chipsets as follows.
 - Pre-PCH (i.e. ICH) chipsets had a maximum frequency of 33 MHz for all
   operations
 - Since Cougar Point the chipsets support dual output fast reads (encoded
   in bit 30).
 - Flash component density encoding has changed from 3 to 4 bits with Lynx
   Point, currently allowing for up to 64 MB chips.

Corresponding to flashrom svn r1843.

Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

Tested mainboards:
OK:
 - ASUS C60M1-I
   http://www.flashrom.org/pipermail/flashrom/2013-February/010578.html
 - ASUS P8H77-I
   http://www.flashrom.org/pipermail/flashrom/2013-March/010607.html
 - ASUS P8H77-M
   http://www.flashrom.org/pipermail/flashrom/2013-May/010994.html
 - ASUS P8P67 LE (B2)
   http://www.flashrom.org/pipermail/flashrom/2013-May/010972.html
 - Elitegroup GeForce6100PM-M2 (V3.0)
   http://www.flashrom.org/pipermail/flashrom/2013-July/011177.html
 - GIGABYTE GA-P55A-UD7
   http://www.flashrom.org/pipermail/flashrom/2013-July/011302.html
 - MSI B75MA-E33 (MS-7808)
   http://www.flashrom.org/pipermail/flashrom/2013-March/010659.html
 - MSI H77MA-G43 (MS-7756)
   http://www.flashrom.org/pipermail/flashrom/2013-April/010853.html
 - MSI KA780G (MS-7551)
   http://paste.flashrom.org/view.php?id=1617
 - SAPPHIRE IPC-E350M1
   Reported by xvilka on IRC
 - Supermicro X8DTG-D
   http://www.flashrom.org/pipermail/flashrom/2013-July/011305.html
NOT OK:
 - ASRock Fatal1ty Z77 Performance
   http://www.flashrom.org/pipermail/flashrom/2013-January/010467.html
 - ASRock Z68 Extreme4
   http://www.flashrom.org/pipermail/flashrom/2013-May/010984.html
 - ASUS P8B75-M LE
   http://www.flashrom.org/pipermail/flashrom/2013-April/010867.html
 - ASUS P8P67-M PRO
   http://www.flashrom.org/pipermail/flashrom/2013-February/010541.html
 - ASUS P8Z68-V LE
   http://www.flashrom.org/pipermail/flashrom/2013-February/010582.html
 - Intel DQ77MK
   http://paste.flashrom.org/view.php?id=1603
 - Supermicro X9DRD-7LN4F
   http://paste.flashrom.org/view.php?id=1582
 - Supermicro X9SCE-F
   http://www.flashrom.org/pipermail/flashrom/2013-February/010588.html
 - Supermicro X9SCM-F
   http://www.flashrom.org/pipermail/flashrom/2013-February/010527.html
 - Tyan S7066
   http://www.flashrom.org/pipermail/flashrom/2013-March/010630.html

Chipsets:
 - Marked Intel B75 as tested
   http://www.flashrom.org/pipermail/flashrom/2013-March/010659.html
 - Marked Intel H77 as tested
   http://www.flashrom.org/pipermail/flashrom/2013-March/010607.html
 - Removed 10de:03e2 because it is apparently the MCP61 host bridge.
   It was reclassified to Host Bridge in the PCI device ID database and there
   is at least one report suggesting this configuration too:
   http://www.flashrom.org/pipermail/flashrom/2012-August/009716.html
 - Added MCP89 which hopefully works with the code for previous versions.
   Thanks to James Laird for submitting this change.

Tested flash chips:
 - Atmel AT25DF641(A) to PREW (+PREW)
   http://www.flashrom.org/pipermail/flashrom/2013-June/011113.html
 - Atmel AT25F512 to PREW (+PREW)
   http://www.flashrom.org/pipermail/flashrom/2013-April/010904.html
   Also, change its ID according to Modification of PCN SC040401A:
   "There has been a change in the returned value of the Product Identification
   (RDID) command, the AT25F512A RDID code is 65h compared to 60h from
   the AT25F512 product."
   It seems to be quite likely that all AT25F512 are fully functional relabeled
   AT25F1024 chips. There are even some hints in the datasheet:
   in table 6 they stress that address pin 16 needs to be low under all circum-
   stances; while continuous reads can wrap around on the AT25F1024 the DS
   notes "For the AT25F512, the read command must be terminated when the
   highest address (00FFFF) is reached." OTOH the lock bit semantics are
   different, but this has not been tested thoroughly
 - Atmel AT25F512A to PREW (+PREW)
   http://paste.flashrom.org/view.php?id=1569
 - Eon EN25F05 to PREW (+PREW)
   http://paste.flashrom.org/view.php?id=1571
 - Macronix MX25L12805(D) to PREW (+REW)
   http://www.flashrom.org/pipermail/flashrom/2013-April/010913.html
 - Spansion S25FL256S......0 and S25FL512S to P/!R!E!W (+P)
   Tested by Stefan Tauner
 - Micron/Numonyx/ST M25PX80 to PREW (+PREW)
   Tested by Stefan Tauner
 - Micron/Numonyx/ST N25Q032..3E and N25Q128..3E to PREW (+PREW)
   Tested by Stefan Tauner
 - Micron/Numonyx/ST N25Q256..3E and N25Q512..3G to P/!R!E!W (+P)
   Tested by Stefan Tauner
 - SST SST25VF040B to PREW (+PREW)
   http://paste.flashrom.org/view.php?id=1574
 - SST SST25VF040B.REMS to PREW (+EW)
   http://paste.flashrom.org/view.php?id=1575
 - ST M25P05-A to PREW (+PREW)
   http://paste.flashrom.org/view.php?id=1576
 - ST M29W512B to PREW (+W)
   http://www.flashrom.org/pipermail/flashrom/2013-March/010635.html
 - Winbond W25Q64.W to PREW (+PREW)
   Tested by the chromiumos guys.
 - Winbond W25Q128.V to PREW (+REW)
   http://www.flashrom.org/pipermail/flashrom/2013-June/011108.html
 - Winbond W25X20 to PREW (+PREW)
   http://www.flashrom.org/pipermail/flashrom/2013-May/010990.html

Miscellaneous:
 - Add Lenovo X201 to the laptop whitelist.
 - Add chip IDs for the ESMT F25L..QA family.
 - Add chip IDs for a few Macronix MX25 models.
 - The list of flashchips is not sorted strictly alphabetically and should not be
   either. Refine the comment explaining the scheme on top of the list.
 - Support -L output of chip sizes with up to 6 decimal places (up to 4 Gb).
 - Use z length modifier in (more) prints for size_t types.
 - Remove chips >16MB again because our current implementation of memory mapping
   the flash chip violates common rules by mapping a window as large as the chip.
   This leads to failing mmaps as can be seen here:
   http://paste.flashrom.org/view.php?id=1695


 - Document spispeed parameter of linux_spi (and fix some leaks).
 - Rephrase the "multiple chips detected" message because it was confusing.
 - Skip verification step if the image is equal to the flash contents.
 - Tiny other stuff.

Corresponding to flashrom svn r1702.

Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Thanks to Idwer and clang for noticing these problems.

Corresponding to flashrom svn r1646.

Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

 - allows for compilation with -Werror=shadow,
 - use extended line limit to fix the most awful line breaks.

Corresponding to flashrom svn r1570.

Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

Tested Mainboards:
OK:
 - ASUS M4A785T-M
   http://www.flashrom.org/pipermail/flashrom/2012-April/009118.html
 - ASUS P5VD2-MX
   http://www.flashrom.org/pipermail/flashrom/2012-March/009014.html
 - ASUS P8Z68-V PRO/GEN3
   http://www.flashrom.org/pipermail/flashrom/2012-April/009086.html
 - Bachmann electronic OT200
   http://www.flashrom.org/pipermail/flashrom/2012-April/009094.html
 - Biostar N61PB-M2S
   http://www.flashrom.org/pipermail/flashrom/2012-March/008958.html
 - GIGABYTE GA-H61M-D2-B3
   http://www.flashrom.org/pipermail/flashrom/2012-March/009002.html
 - MSI MS-7740 (H61MA-E35(B3))
   http://www.flashrom.org/pipermail/flashrom/2012-March/008985.html
 - Tyan S2875 (Tiger K8W)
   http://www.flashrom.org/pipermail/flashrom/2012-March/008986.html
 - ZOTAC nForce 630i Supreme (N73U-Supreme)
   http://www.flashrom.org/pipermail/flashrom/2012-April/009073.html
 - ZOTAC ZBOX AD02 (PLUS)
   http://www.flashrom.org/pipermail/flashrom/2012-April/009047.html
NOT OK:
 - ASRock H67M
   http://www.flashrom.org/pipermail/flashrom/2012-March/008909.html
 - ASUS P8P67 LE
   http://paste.flashrom.org/view.php?id=1097
 - ASUS Maximus IV Extreme
   http://www.flashrom.org/pipermail/flashrom/2012-March/009033.html
 - Biostar H61MU3
   http://www.flashrom.org/pipermail/flashrom/2012-February/008832.html
 - Biostar M7VIQ
   http://www.flashrom.org/pipermail/flashrom/2012-February/008863.html
 - Dell Inspiron 580
   http://www.flashrom.org/pipermail/flashrom/2012-March/008888.html
 - Dell Vostro 460
   http://www.flashrom.org/pipermail/flashrom/2012-April/009144.html
 - Fujitsu-Siemens CELSIUS W410 (D3062-A1)
   http://www.flashrom.org/pipermail/flashrom/2012-March/008987.html
 - EPoX EP-3PTA
   http://www.flashrom.org/pipermail/flashrom/2012-April/009043.html
 - HP XW6400
   http://www.flashrom.org/pipermail/flashrom/2012-March/009006.html
 - HP XW9300
   http://www.flashrom.org/pipermail/flashrom/2012-February/008862.html
 - Intel DG965OT
   http://paste.flashrom.org/view.php?id=1096
 - Intel DN2800MT (Marshalltown)
   http://www.flashrom.org/pipermail/flashrom/2012-April/009095.html
 - Lenovo T420
   http://paste.flashrom.org/view.php?id=1095
 - Lenovo X1
   http://www.flashrom.org/pipermail/flashrom/2012-April/009135.html
 - MSI GF615M-P33
   http://www.flashrom.org/pipermail/flashrom/2012-March/008956.html

Tested flash chips:
 - mark EN25Q32(A/B) as TEST_OK_PROBE (+P)
   http://www.flashrom.org/pipermail/flashrom/2012-February/008832.html
 - mark S25FL032A as TEST_OK_PR (+PR)
   http://www.flashrom.org/pipermail/flashrom/2012-April/009105.html
 - mark AT25DF161 as TEST_OK_PROBE (+P)
   http://www.flashrom.org/pipermail/flashrom/2012-April/009095.html
 - mark SST as TEST_OK_PREW (+EW)
   http://www.flashrom.org/pipermail/flashrom/2012-April/009094.html

Tested chipset enables:
 - H61 (various reports)
 - SiS 755
   http://www.flashrom.org/pipermail/flashrom/2012-April/009072.html

 - Fix compilation of ich_descriptor_tool which was broken since r1492.
 - Add Documentation regarding unlocking the ME region on Intel chipsets.
 - Fix reading the flash descriptor via FDOC/FDOD and prettyprinting of the
   descriptor on boards with 5 active regions.
 - Reorder some boards in print.c.
 - Add Intel 7 Series (Panther Point) PCI IDs.
 - Add preliminary PCI IDs for future Intel chipsets (DH89xxCC and Lynx Point)
   see https://lkml.org/lkml/2012/2/20/467


 - Change the message for untested chipsets to send only after an attempt to
   update the firmware with flashrom.
 - Fix warnings in ich_descriptor_tool's build.

Corresponding to flashrom svn r1524.

Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

This patch adds an external utility that shares most of the existing descriptor
decoding source code. Additionally to what is available via FDOC/FDOD this
allows to access:
 - the softstraps which are used to configure the chipset by flash content
   without the need for BIOS routines. on ICH8 it is possible to read those
   with FDOC/FDOC too, but this was removed in later chipsets.
 - the ME VSCC (Vendor Specific Component Capabilities) table. simply put,
   this is an SPI chip database used to figure out the flash's capabilities.
 - the MAC address stored in the GbE image.

Intel thinks this information should be confidential for ICH9 and up, but
references some tidbits in their public documentation.
This patch includes the human-readable information for ICH8, Ibex Peak
(5 series) and Cougar Point (6 series); the latter two were obtained from
leaked "SPI Flash Programming Guides" found by google. Data regarding ICH9
and 10 is unknown to us yet. It can probably found in:
"Intel® ICH7, ICH8, ICH9 and ICH10 — SPI Family Flash Programming Guide"
Information regarding the upcoming Panther Point chipset is also not included.

Corresponding to flashrom svn r1480.

Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Matthias Wenzel <bios@mazzoo.de>

This was done to ease the review. Another patch will hook up (and
explain) this code later.

Corresponding to flashrom svn r1452.

Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Based on the work of Matthias 'mazzoo' Wenzel this patch adds pretty
printing of those ICH/PCH flash descriptor sections that are
cached/mapped by the chipset (and which are therefore reachable via
FDOC/FDOD registers).

this includes the following:
- content section:
    describes the image and some generic properties (number of
    sections, offset of sections, PCH/ICH and MCH/PROC strap
    offsets and lengths)
- component section:
    identify the different SPI flash chips and their capabilities.
- region section
    similarly to a partition table this describes the different regions.
    the content of FLREG* is derived from this section.
- master section
    defines SPI master (host, ME, GbE) access rights of the
    individual regions. the content of PR* is derived from this section.

this is only a part of the data included in the descriptor. other
information can be retrieved from a complete binary dump of the
descriptor region only.

this patch also adds macros and pretty printing for "Vendor Specific
Component Capabilities" registers: there are two of them: lower and
upper. they describe the properties of the address space divided by
FPBA (which allows to use multiple flash chips or partitions with
different properties). the properties of all supported flash chips
(together with their RDIDs) are stored in the same format in table
in a descriptor section (which is used by the ME apparently). a
later patch will use the macros outside of ichspi.c which is the
reason why the prettyprinting function and the register bit macros
are not defined in ichspi.c but ich_descriptors.h (else they would
be moved in the follow-up patch).

because this patch relies on (compiler) implementation-specific
layouting of bit-fields, it checks for correct layout before taking
any action on runtime.

Corresponding to flashrom svn r1443.

Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>