package-needs-versioned-debhelper-build-depends 13"

uploaders: Jeremiah C. Foster <jeremiah.foster@puri.sm> (field must be
empty)

Removing util/getrevision.sh since Debian does't use it either
Looks like we have to have util/getrevision.sh if we want a version from the binary.

It was indented with two spaces instead of one tab. Fix it.

Change-Id: I18051ae4433b267b9552a034a67d7830b9206c20
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41776


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

This allows flashrom to build with GCC 10.

Change-Id: I2166cdf3681452631ef8e980face2924e9a6c81a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41775


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>

With this change flashrom can detect, enable and flash on this board
both under vendor BIOS and coreboot.

Change-Id: I395ff50fbcda8ecdaa26033f0d99b2b0eb42f7ff
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41354


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Change-Id: I5d511d7ec254bdbd9926e6d8efc308fb2339cb81
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38661


Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

When hardware write protect is applied, flashrom crashed and
generate coredump. spi_disable_blockprotect_generic() calls
flash->chip->printlock() method when disable was failed,
but this method is optional, can be NULL depends on type of
flashrom chip. NULL pointer check before call is added to
avoid crash.

BRANCH=none
BUG=b:129083894
TEST=Run on Mistral P2
(On CR50 console, run "wp disable")
flashrom --wp-range 0 0x400000
flashrom --wp-enable
(On CR50 console, run "wp enable")
flashrom -r /tmp/test.bin
Verify "Block protection could not be disabled!" is shown,
but flash read completes.
Signed-off-by: Yuji Sasaki <sasakiy@chromium.org>

Change-Id: I81094ab5f16a85871fc9869a2e285eddbbbdec4e
Reviewed-on: https://chromium-review.googlesource.com/1535140


Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: SANTHOSH JANARDHANA HASSAN <sahassan@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40468


Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Enables the USB SPI transfer retry mechanism when the error code
USB_SPI_WRITE_COUNT_INVALID is returned. This error code can
indicate a recoverable USB transfer failure.

BUG=b:153887087
BRANCH=none
TEST=Manual testing of ServoMicro and Flashrom when performing
    reads, writes, and verification of the EC firmware on Nami.
TEST=Modified ServoMicro to randomly corrupt USB packets when
    reading the packet length to replicate bad packets and the
    verify recovery is successful.

Change-Id: I9e6b2ccec0b06aab0d6920f1bddf108058e5d6b1
Signed-off-by: Brian J. Nemec <bnemec@chromium.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41152


Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Turns out the MST likely doesn't need these so-called defaults
to be written for the purposes of spi flashing.

BUG=b:152558985,b:148745673
BRANCH=none
TEST=builds

Change-Id: Ieb938cf0805b22692d61db23795208c9be962b60
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41124


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>

Chip erasures take much longer than sector and bank
erasures. Allow the wait loop helper to multiply the
max timeout in this very specific case while quickly
timeout for other ops that are expected to be shorter.

V.2: Fix nonsense fall though warn-err

BUG=b:152558985,b:148745673
BRANCH=none
TEST=flashrom -p realtek_mst_i2c_spi:bus=8 -E &&
     flashrom -p realtek_mst_i2c_spi:bus=8 -w foo
    (cycle)..

Change-Id: I4a36aa3101827e69eb244775d25bbb476d4bb780
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41123


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>

Turns out broken erasures highlighted some of the issues
in the write256 implementation. After a fair amount of
time deciphering scarce documentation details a correct
implementation was finally derived.

V.2: Rename 'start_program() -> execute_write()' to
  clarify the intention and not to overload the term
  'program' since the MST actually runs a 'program'
  itself.

BUG=b:152558985,b:148745673
BRANCH=none
TEST=flashrom -p realtek_mst_i2c_spi:bus=8 -E &&
  flashrom -p realtek_mst_i2c_spi:bus=8 -w foo &&
  flashrom -p realtek_mst_i2c_spi:bus=8 -r foo &&
  hexdump -C foo

Change-Id: If61ff95697f886d3301a907b76283322c39ef5c7
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41080


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>

Before issuing SPI opcodes into 0x61 the top three BITS of
0x60 need to be carefully crafted. Correctly craft these
in the case of SPI erasures and document this registers
expectations. Clean up remaining debug comments while we
are here.

BUG=b:152558985,b:148745673
BRANCH=none
TEST=flashrom -p realtek_mst_i2c_spi:bus=8 -E  &&
  flashrom -p realtek_mst_i2c_spi:bus=8 -r foo &&
  hexdump -C foo

Change-Id: Ib11ba8f63b11a1c5ebaa68deb7971648de8c2ecd
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41079


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>

Change-Id: Ib9d99fefda812d20265db47be353c844f8b77129
Found-by: Coverity Scan #1420204
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40969


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

If the transfer failed, the data might be invalid.

Change-Id: I3ad9daa00a54e2a3954983cec91b6685f1a98880
Found-By: Coverity Scan #1405870
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40970


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

The Chromium flashrom fork has very poor dispatch logic whereas
upstream has proper inversion of control with a generic 'data'
void * member to stuff long-lived state in. Leverage the member
to store the USB descriptor state in during the life-time of the
spi master.

V.2: Remove unnecessary indirection as is the case in
  commit a25c13cd.

BUG=b:140394053
BRANCH=none
TEST=builds && detects flashchip name.

Change-Id: Ida9dce97fef2c6dfd68a278c879917fdd3ff7fef
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40105


Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Try to document some of the register magics with plausible
names for readability.

BUG=b:152558985,b:148745673
BRANCH=none
TEST=builds

Change-Id: I97313f6f14438e4cbfc62faa7242cf6fc271f387
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41022


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Since lspcon talks over i2c I doubt libusb is a build
requirement, remove it.

Change-Id: Ic4d71c10d2d8c0c881aa5732daed35c20d905a5e
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41020


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>

This spi master allows for programming of a Realtek RTD2142
MST with external SPI flash chip routed via its internal i2c
transport mechanism.

BUG=b:152558985,b:148745673
BRANCH=none
TEST=echo "00000000:0004ffff fw" > layout && \
  flashrom -p realtek_mst_i2c_spi:bus=8 -l layout -i fw:dump.bin -r && \
  flashrom -p realtek_mst_i2c_spi:bus=8 -l layout -i fw:dump.bin -w && \
  flashrom -p realtek_mst_i2c_spi:bus=8 --flash-size && \
  flashrom -p realtek_mst_i2c_spi:bus=8 --flash-name

Change-Id: I892e0be776fe605e69fb39c77abf3016591d7123
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40667


Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Shiyu Sun <sshiyu@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

As we want to allocate an array of `flashrom_board_info` structs, use
that type in sizeof. This did not cause problems as `board_info` was at
least as big as `flashrom_board_info`, but nothing guarantees it.

Change-Id: I66e875d54c9a7cc59898b072b052282b0b5cbb2f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39973


Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Intel document #336067 uses `BIOS Control` to refer to this register.

Change-Id: Ib66547b2b5d77658ab1925e4ad3acfe44e14843c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40857


Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

This reverts commit a3519561.

Breaks support for most SPI flash chips. It's too big and too
invasive to be reviewed as a single commit.

The changes to `spi_poll_wip():spi25.c` were not noticed in the
original review that were from the similarly named function and
file `s25f_poll_status():s25f.c` in the downstream Chromium fork.

V.2: Rebase and rephrase commit msg to reflect how the issue
     slipped in.

Change-Id: Id2a4593bdb654f8a26957d69d52189ce61621d93
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40626


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shiyu Sun <sshiyu@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>