Like in 1ef2917d

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

like in f53705fd

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

We don't have anything feeding these and they cause trouble when
rebasing on linux-next so drop them.

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

from NXPs kernel

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

We don't need it atm.

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

This is just a hack until we have a proper solution. We don't want
to allow userspace patch all kernel space.

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

0x14000 and 0x14018 are SRC_ADDR and DEST_ADDR in the BLT engine.
0x15C00 are the TX_DESCRIPTOR addresses on Halti5 at least.

This avoids the etnaviv_warn_if_non_sensitive warnings.

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

Otherwise we might end up with modules that can't be loaded:

  modprobe: ERROR: could not insert 'goodix': Unknown symbol in module, or unknown parameter (see dmesg)
  [   15.190397] goodix: Unknown symbol touchscreen_report_pos (err -2)
  [   15.221560] goodix: Unknown symbol touchscreen_parse_properties (err -2)
  [   64.677545] goodix: Unknown symbol touchscreen_report_pos (err -2)
  [   64.683767] goodix: Unknown symbol touchscreen_parse_properties (err -2)

Signed-off-by: Guido Günther <agx@sigxcpu.org>

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

The mainline ATF doesn't currently support the FSL_SIP_GET_SOC_INFO call
nor does it have the code to identify different imx8mq SOC revisions so
mimic what NXPs ATF does here.

As a fallback use ATF so we can identify new revisions once it gains
support or when using NXPs ATF.

Signed-off-by: Guido Günther <agx@sigxcpu.org>

This adds initial support for the NWL MIPI DSI Host controller found on
i.MX8 SoCs.

It adds support for the i.MX8MQ but the same IP can be found on
i.MX8QXP.

It has been tested on the Librem 5 devkit using DCSS.

Co-developed-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Guido Günther <agx@sigxcpu.org>

The Northwest Logic MIPI DSI IP core can be found in NXPs i.MX8
Socs.

Signed-off-by: Guido Günther <agx@sigxcpu.org>

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

Signed-off-by: Guido Günther <guido.gunther@puri.sm>

During the i2c probe the clock must be active

Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

Need to be able to enable the camera so use a named gpio-led
instead of an unnamed gpio.

Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

Enable sound support for the devkit including the modem

Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

Connect the WoWWAN signal to a gpio key to wake the system

Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

Use the 3v3 peripheral regulator instead of the pwr_en one

Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

Specify all of the mclk's for the sai interfaces.

Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

Set ausio PLL1 and PLL1 to use the correct parents

Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

Enable the sai6 interface.

Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

Add the simcomm modem and the sai6 interface that connects it.

Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

SAI module on imx7ulp/imx8m features 2 new registers (VERID and PARAM)
at the beginning of register address space.

On imx7ulp FIFOs can held up to 16 x 32 bit samples.
On imx8mq FIFOs can held up to 128 x 32 bit samples.

Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>

New IP version introduces Version ID and Parameter registers
and optionally added Timestamp feature.

VERID and PARAM registers are placed at the top of registers
address space and some registers are shifted according to
the following table:

Tx/Rx data registers and Tx/Rx FIFO registers keep their
addresses, all other registers are shifted by 8.

SAI Memory map is described in chapter 13.10.4.1.1 I2S Memory map
of the Reference Manual [1].

In order to make as less changes as possible we attach an offset
to each register offset to each changed register definition. The
offset is read from each board private data.

[1]https://cache.nxp.com/secured/assets/documents/en/reference-manual/IMX8MDQLQRM.pdf?__gda__=1563728701_38bea7f0f726472cc675cb141b91bec7&fileExt=.pdf



Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>

This allows combining multiple-data-line FIFOs into a
single-data-line FIFO.

Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>

FIFO combining mode allows the separate FIFOs for multiple data channels
to be used as a single FIFO for either software accesses or a single data
channel or both.

FIFO combined mode is described in chapter 13.10.3.5.4 from i.MX8MQ
reference manual [1].

For each direction (RX/TX) fifo combine mode is read from fsl,fcomb-mode
DT property. By default, if no property is specified fifo combine mode
is disabled.

[1]https://cache.nxp.com/secured/assets/documents/en/reference-manual/IMX8MDQLQRM.pdf?__gda__=1563728701_38bea7f0f726472cc675cb141b91bec7&fileExt=.pdf



Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>

SAI supports up to 8 data lines. This property let the user
configure how many data lines should be used per transfer
direction (Tx/Rx).

Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>

SAI supports up to 8 Rx/Tx data lines which can be enabled
using TCE/RCE bits of TCR3/RCR3 registers.

Data lines to be enabled are read from DT fsl,dl_mask property.
By default (if no DT entry is provided) only data line 0 is enabled.

Note:
We can only enable consecutive data lines starting with data line #0.

Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>

Tx channel enable (TCE) / Rx channel enable (RCE) bits
enable corresponding data channel for Tx/Rx operation.

Because SAI supports up the 8 channels TCE/RCE occupy
up the 8 bits inside TCR3/RCR3 registers we need to extend
the mask to reflect this.

Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>

SAI IP supports up to 8 data lines. The configuration of
supported number of data lines is decided at SoC integration
time.

This patch adds definitions for all related data TX/RX registers:
	* TDR0..7, Transmit data register
	* TFR0..7, Transmit FIFO register
	* RDR0..7, Receive data register
	* RFR0..7, Receive FIFO register

Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>

The DMA request schould be triggered as soon as the FIFO has space
for another burst. As different versions of the SAI block have
different FIFO sizes, the watrmark level needs to be derived from
version specific data.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

New revisions of the SAI IP block have even more differences that need
be taken into account by the driver. To avoid sprinking compatible
checks all over the driver move the current differences into of_match_data.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Initial cut of the phone defconfig

Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>

Initial cut of the phone devicetree

Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>