enable cpufreq and add cpuidle workaround
Closed
requested to merge martin.kepplinger/linux-next:i/imx8-5.2-rc7-devkit/cpufreq_cpuidle into imx8-5.2-rc7-devkit
- Jul 09, 2019
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This is not currently needed, instead a platform device is always created from SOC-specific code. We can use of_machine_is_compatible for per-SOC behavior instead. Suggested-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
bb3b4c14 -
Early samples without fuses written report "0 0" which means consumer segment and minimum speed grading. According to datasheet the minimum speed grade is not supported for consumer parts so all OPPs are disabled which results in stack dumps later on. Fix by clamping minimum consumer speed grade to 1 on imx8mm and imx8mq. Fixes: 4d28ba1d ("cpufreq: Add imx-cpufreq-dt driver") Signed-off-by:
b9c9c291 -
Martin Kepplinger authored
Using pm_qos results in (imx8mq) cpus never being able to reach the cpu-sleep C-state, see https://lwn.net/Articles/384146/ for some background. The pm_qos API is very rarely used in general. Signed-off-by:
8d115854 -
For imx8m we need a separate small driver to read "speed grading" information from fuses and determine which OPPs are supported. Signed-off-by:
a7644a84 -
Right now in upstream imx8m cpufreq support just lists a common subset of OPPs because the higher ones should only be attempted after checking speed grading in fuses. Add a small driver which checks speed grading from nvmem cells before registering cpufreq-dt. This driver allows unlocking all frequencies for imx8mm and imx8mq and could be applied to other chips like imx7d Signed-off-by:
381e02eb -
Martin Kepplinger authored
remember we need the following changes in ATF too: https://github.com/abelvesa/arm-trusted-firmware/tree/imx8mq-err11171 Signed-off-by:
7acb4163 -
Add the cpu-sleep idle state with all the necessary parameters and also add the cpu-idle-states to the cpu nodes. The 'broken-wake-request-signals' property is used to let the irq-imx-gpcv2 driver know that the wake request signals from GIC are not linked to the GPC at all and, therefore, the driver should make use of the dedicated workaround to explicitly wake up the target core on every IPI. Signed-off-by:8df72b53 -
Add nvmem-cells reference to cpu and fill the OPP table with all known OPPs. Signed-off-by:
f5de5283
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- Jul 08, 2019
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i.MX8MQ is missing the wake_request signals from GIC to GPCv2. This indirectly breaks cpuidle support due to inability to wake target cores on IPIs. Here is the link to the errata (see e11171): https://www.nxp.com/docs/en/errata/IMX8MDQLQ_0N14W.pdf Now, in order to fix this, we can trigger IRQ 32 (hwirq 0) to all the cores by setting 12th bit in IOMUX_GPR1 register. In order to control the target cores only, that is, not waking up all the cores every time, we can unmask/mask the IRQ 32 in the first GPC IMR register. So basically we can leave the IOMUX_GPR1 12th bit always set and just play with the masking and unmasking the IRO 32 for each independent core. Since EL3 is the one that deals with powering down/up the cores, and since the cores wake up in EL3, EL3 should be the one to control the IMRs in this case. This implies we need to get into EL3 on every IPI to do the unmasking, leaving the masking to be done on the power-up sequence by the core itself. In order to be able to get into EL3 on each IPI, we 'hijack' the registered smp cross call handler, in this case the gic_raise_softirq which is registered by the irq-gic-v3 driver and register our own handler instead. This new handler is basically a wrapper over the hijacked handler plus the call into EL3. To get into EL3, we use a custom vendor SIP id added just for this purpose. All of this is conditional for i.MX8MQ only. Signed-off-by:
24aa2c09
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