This reverts commit a3519561.

Breaks support for most SPI flash chips. It's too big and too
invasive to be reviewed as a single commit.

The changes to `spi_poll_wip():spi25.c` were not noticed in the
original review that were from the similarly named function and
file `s25f_poll_status():s25f.c` in the downstream Chromium fork.

V.2: Rebase and rephrase commit msg to reflect how the issue
     slipped in.

Change-Id: Id2a4593bdb654f8a26957d69d52189ce61621d93
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40626


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shiyu Sun <sshiyu@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Replace log lines with the prefix formatter '%s: ..' and pass
'__func__' to the printers so that errors are prefixed with the
function from which they originated.

BUG=b:154285774
BRANCH=none
TEST=build success

Change-Id: If3205d8e453cfcd37f725b4fd135fe1221c913c0
Signed-off-by: Shiyu Sun <sshiyu@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40901


Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

The ChromiumOS flashrom fork has since const'ify flashctx
in a few places. This aligns the function signatures to
match with downstream to ease forward porting patches
out of downstream back into mainline flashrom.

This patch is minimum viable alignment and so feedback is
welcome.

Change-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40324


Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

If `buf` became NULL because of an error, subsequent calls to the
`ft2232_spi_send_command` function with a smaller buffer size will
result in a null pointer dereference. Add an additional null check
before using `buf` to prevent that. Moreover, use `size_t` for the
`bufsize` and `oldbufsize` variables, as it's what `realloc` uses.

Change-Id: Idc4237ddca94c42ce2a930e6d00fd2d14e4f125c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39975


Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Change-Id: I5fcc23d81b8404af90768afa2954509bf334ab2c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39974


Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Change-Id: I0675b467d7b0d24626a336033668bf80bfeeb815
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40679


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>

Change-Id: I08c0612f3fea59add9bde2fb3cc5c4b5c3756516
Found-by: Coverity Scan #1412744
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40653


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>

Change-Id: Ic650b43395c64b1677f6e114b0faf42a3b7b3759
Found-by: Coverity Scan #1415214
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40652


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>

Change-Id: I19c91ae881895ecc4ea85dcfd40a69bb58289a60
Found-by: Coverity Scan #1420203
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40651


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>

Change-Id: I2701a8fbae63657edc9cc258666cc951f92b1115
Found-by: Coverity Scan #1420204
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40650


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>

Change-Id: I6eea3e34ed6fc5d3fe65d5cf7e7bfc5e571bfa73
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40576


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

This may seem too big just to support yet another flash chip, but in
reality it brings support for whole new family of S25FS
Spansion/Cypress flash chips. These chips require handling of some
special status registers for erasing or writing, with very specific
timing checks in place.

For example, WIP status bit will remain being set to 1 if erase or
programming errors occur, and in that case chip 'software reset' has
to be performed otherwise the chip will remain unresponsive to all
further commands. Also, special CR3NV register (Configuration Register
3 Nonvolatile) status bits needs to be read and set by using RDAR
(ReaD Any Register) and WRAR (WRite Any Register) OP commands, and
these states are needed to determine which type of reset feature is
enabled at the time (legacy or S25FS type) in the first place,
determine whether Uniform or Hybrid sector architecture is used
at the time, or set programming buffer address wrap point (256 or 512
bytes). Furthermore, S25FS chip status register has to be restored to
its original state (hence that ugly CHIP_RESTORE_CALLBACK) following
erasing or writing, failing to do so may result in host being unable
to access data on the chip at all.

Finally, although this brings support for the whole family of chips,
I only have one such chip to do the actual testing, S25FS128S (Small
Sectors), which I had fully tested on ch341a and FT4232H programmers,
with confirmed working probe, read, erase and write.

Full summary of changes are here:

flashchips:
  add new flashchip sctructure property:
    .reset
  add chip definitions:
    S25FS128S Large Sectors
    S25FS128S Small Sectors

flash:
  add macro (chip_restore_func_data call-back):
    CHIP_RESTORE_CALLBACK

flashrom:
  add struct:
    chip_restore_func_data
  add call-back function:
    register_chip_restore

spi:
  add OP codes:
    CMD_RDAR, CMD_WRAR, CMD_WRAR_LEN, CMD_RSTEN, CMD_RST
  add register bit function definitions:
    CR3NV_ADDR, CR3NV_20H_NV
  add timers:
    T_W, T_RPH, T_SE

spi25:
  refactor (based on chromiumos implementation) function:
    spi_poll_wip
  port these functions from chromiumos:
    probe_spi_big_spansion
    s25fs_software_reset
    s25f_legacy_software_reset
    s25fs_block_erase_d8

spi25_statusreg:
  port these functions from chromiumos:
    spi_restore_status
    s25fs_read_cr
    s25fs_write_cr
    s25fs_restore_cr3nv

Most of the ported functions are originally from s25f.c found at
https://chromium.googlesource.com/chromiumos/third_party/flashrom


with exception of spi_restore_status which is defined in
spi25_statusreg.c. The rest of macros and OP codes are defined in
same files as in this commit.

Change-Id: If659290874a4b9db6e71256bdef382d31b288e72
Signed-off-by: Samir Ibradzic <sibradzic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39822


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>

Clean up some confusion of implicit copies by indirection.
This allows the caller of register_spi_master() to have it's
internal state in the expected way.

Also add an error when the mpu reset fails on init.

BUG=b:148746232,b:153027771,b:140394053
BRANCH=none
TEST=builds

Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Change-Id: I66ba4ffeb696309b8ad5b5ba58650630e8feefa9
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40470


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Commit 92d6a861 ("Refactor Intel Chipset Enables") eliminated a check
to disable SPI when ICH7 has booted from LPC, as the hardware does not
support it. Therefore, when flashrom probes the SPI bus, it times out
waiting for the hardware to react, for each and every SPI flash chip.
This results in very long delays and countless instances of the error:

    Error: SCIP never cleared!

To prevent this, bring back part of the lost check. Probing for LPC and
FWH when booted from SPI does not seem to cause any problems on desktop
mainboards with ICH7, so don't disable LPC nor FWH if that is the case.

Tested on ECS 945G-M4 (ICH7, boots from LPC), works without errors.

Change-Id: I5e59e66a2dd16b07f2dca410997fce38ab9c8fd1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40401


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>

If the `--flash-contents` switch is specified more than once, it will
result in a memory leak. Therefore, allow this option only once.

Change-Id: I530933c9a6431580fe4645396bb363939472a80a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39972


Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

BUG=b:153515968
BRANCH=kukui
TEST=flash coreboot on kakadu and get successful result.

Change-Id: I8637129421a3b0f96bd8dffa4f50783ea6931967
Signed-off-by: Scott Chao <scott.chao@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40275


Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: Edward O'Callaghan <quasisec@chromium.org>

https://www.winbond.com/resource-files/W25Q512JV%20DTR%20RevB%2006132019%20133.pdf



Tested with dediprog SF100.

Change-Id: I8d16f0918785795cc49500435a03641b87d706e9
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34595


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

This is to really make use of page write time advantage.
Because the Chunksize must be 256Byte raw data plus the address and cmd bytes.

For details check:
https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/message/W2HULJTDPHWPBZY6MLM6TGT7RTHSGHON/



Signed-off-by: Simon Buhrow <simon.buhrow@posteo.de>
Change-Id: Iac067a23025e9df053ab9cd4e82a98de70046c18
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39632


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

This adds support for the Parade lspcon usb-c to HDMI protocol
translater part that is i2c-controlled. The support allows the
host to reach the SPI ROM that hangs off the part where it
stores its firmware.

Usage is as follows:
	flashrom -p lspcon_i2c_spi:bus=X
	where X is the bus number.

BUG=b:148746232
BRANCH=none
TEST=tested with following commands, read/write/erase works good.
	flashrom -p lspcon_i2c_spi:bus=7 -r /tmp/foo;
	flashrom -p lspcon_i2c_spi:bus=7 -E;
	flashrom -p lspcon_i2c_spi:bus=7 -w /tmp/foo;

Change-Id: I039e683252cfaf1ffef8694a3e8081b1b6b944f7
Signed-off-by: Shiyu Sun <sshiyu@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39687


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>

See https://www.kernel.org/doc/Documentation/i2c/

 for details.

This creates common interface for I2C access functions, and adds
implementation for linux I2C functions.

BUG=b:148746232
BRANCH=none
TEST=build success

Signed-off-by: Shiyu Sun <sshiyu@chromium.org>
Change-Id: Ie0487824dfb71970bede17f617dbbb30ddf78c12
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39686


Tested-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>

Turns out CONFIG_RAIDEN was missing in the LIBUSB1
as no overrides. Credit to HAOUAS Elyes for spotting this.

Change-Id: I7dd26665a0133175949c11717837e9de68a1bf71
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39896


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>

Change-Id: I7ba768abfa6f19f23379e5f47a6bc099fc01d3da
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39780


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>

The raiden_debug programmer is of type USB. However, it does not set the
field `devs.dev`, which will result in a segfault when trying to print
the devices of the non-existing table.

Fix that by replacing `devs.note` with `devs.dev` and adding an empty
device table. Since Device IDs are not used to match programmers,
nothing could be added to the table.

TEST=Running `flashrom -L` no longer segfaults and returns normally.

Change-Id: Ie4171a11384c34abb102d1aadf86aa1b8829fc04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39826


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Support GD25WQ80E, which is the internal flash of IT81202.

TEST=Building flashrom and flashing FW image into IT81202 successfully.

Change-Id: Ib5feaa6ecc7b11b2218e5f02c087b4331388bef8
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39820


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>

32Mbit (4MiB) [x1/x2/x4] Wide Voltage Range (VCC 1.65V-3.6V). It is
similar to the already-supported MX25R6435F, but the total size is
halved.

Tested on ch341a, FT4232H and FT2232H (PicoTAP) programmers, confirmed
working probe, read, erase and write.

Fixes: https://github.com/flashrom/flashrom/issues/43



Change-Id: I6e79115adba17d13d24bc85d78707d53fd4a0be5
Signed-off-by: Samir Ibradzic <sibradzic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39532


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Tested reading and writing on a Samsung laptop (see CB:39388).

Change-Id: Idbb9c719a6f794a35293bb3b167cc1491d24d4fa
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39389


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Tested reading, writing and erasing the internal flash chip using an
Acer Aspire ES1-572 laptop with an Intel i3-6006U. However, since all
ME-enabled chipsets are marked as DEP instead of OK, this one shall
follow suit as well.

Change-Id: Ib8ee9b5e811df74d2f48bd409806c72fe862bc24
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39173


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>

Add a delay following the AP and EC flash enable requests. This allows
any power rails enabled by these signals to settle and to meet the power
on to first SPI write timing requirements.

Forward ports the downstream commit:
   https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2036738



Change-Id: I4c1777777ee67580605c6e6f4c0c228cccc392c7
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39312


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Forward ports the downstream commit:
 https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2073077



Change-Id: I77def28040fea8d1ecf102463180378f8612b00e
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39311


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

This overcomes a problem with the ServoMicro where USB packets can be
ack'd by the device without triggering interrupts or loading data into
the USB endpoints. The retry mechanism attempts the USB read 3 times
before reattempting the write call to avoid performing multiple SPI
transfers due to a USB problem. This process repeats 3 times before we
return the last error code. Intermediary problems are reported in the
status code.

Based off the downstream commit:
  https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2038271



Change-Id: I76cde68852fa4963582d57c7dcb9f24de32c6da8
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39310


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

 - The USB SPI interface has been split up into write and read stages.
 - The packet packing has been transitioned from array based to a
   struct.

This was based off the downstream commit:
  https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2036508



Change-Id: Id3a2a544c1c7e1d969a5157977b8a1c7af18371b
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39309


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Change-Id: I414d6e5fcb590a006dd53fa93df80ec2a765c5d1
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39308


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

This only sets 3rd CS# bit be asserted during read/write operations.

Tested and confirmed working on 4232H & PicoTap ft2232 programmers
against MX25R6435F & S25FL128S chips.

Signed-off-by: Samir Ibradzic <sibradzic@gmail.com>
Change-Id: Ia0ac14b9a52f251306887500dae3e57d73322157
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38898


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>

This allows multiple 'csgpiol' bits to be set to active state at the
same time. Previously, only one GPIOL could be activated. I have an
use-case such that FT4232H is wired to two different SPI chips, and in
order to select one of them two GPIOLs have to be set.

Now, one can enable any particular GPIOL, for example:

csgpiol=01

would activate GPIOL0 and GPIOL1 at the same time.

The change is backward-compatible with previous csgpiol formatting.

Signed-off-by: Samir Ibradzic <sibradzic@gmail.com>
Change-Id: I645ddaa9852e9995bd2a6764862fda2b2ef0c26b
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38705


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Added spireadmode for >= Bolton.
Do not override speed or read mode for >= Bolton if parameter not
specified.
Minor cleanup of sb600spi.c code.

TEST=Manual: deploy on tremblye read flash using various parameters
BUG=b:147665085,b:147666328
BRANCH=master

Change-Id: Id7fec7eb87ff811148217dc56a86dca3fef122ff
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38833


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Initial check-in of the Raiden debugger programmer.

Squash in,
  raiden_debug: Add missing .write_aai cb fn
  raiden_debug: greatly improve protocol documentation

BUG=b:143389556
BRANCH=none
TEST=builds

Change-Id: Ifad273a708acea4de797a0808be58960635a8864
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38209


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

These are helpful usb device accessors and helpers that
are later used for the so-called Raiden debugger programmer.

BUG=b:143389556
BRANCH=none
TEST=builds

Change-Id: Ic928220fc919fe4958c8150e61e11470dac88f13
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38936


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

The following is a E2E tester for a specific chip/chipset
combo. The tester itself is completely self-contained and
allows the user to specify which tests they wish to preform.
Supported tests include:

 - chip-name
 - read
 - write
 - erase
 - wp-locking

Change-Id: Ic2905a76cad90b1546b9328d668bf8abbf8aed44
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38951


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>

This modifies CB:23025 further to work with upstream as it is now,
without the syntax changes in the patch chain. I also gave it a new
name since this script is, well, uber.

Since flashrom currently only supports reading/writing ROM-sized files
we can't easily determine a targeted region offset and size except
when a layout file is used. Therefore, some extra arithmetic is needed
in the partial write test and the only modes allowed are clobber mode
and layout mode.

A few other changes:
- Update paths and script name
- Remove write-protect testing support
- Use ROM-sized files only, no region-sized files
- Return error if flashmap or ifd mode are used

Documentation is ported from https://goo.gl/3jNoL7

 into a markdown
file and accompanying SVGs. Minor changes were made for clarity and
formatting, and references to write protect testing have been removed
for the time being.

Tested using a Raspberry Pi with a W25Q16

Change-Id: I1af55d5088c54ee33853009797adbd535a506b49
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38788


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>

As found on the Tesla AP2.5 board.

Based on https://mail.coreboot.org/pipermail/flashrom/2013-June/011066.html



Tested with:
    flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=512 -r content.bin

Signed-off-by: Bernhard Urban-Forster <lewurm@gmail.com>
Change-Id: Ifa9b7615951125b6bbc1f051370ef54896bf506c
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38596


Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>